devLib2  2.11
Macros
VME CSR Register Definitions

Macros

#define CR_ROM_CHECKSUM   0x0003
 8-bit checksum of Configuration ROM space More...
 
#define CR_ROM_LENGTH   0x0007
 Number of bytes in Configuration ROM to checksum. More...
 
#define CR_DATA_ACCESS_WIDTH   0x0013
 Configuration ROM area (CR) data access method. More...
 
#define CSR_DATA_ACCESS_WIDTH   0x0017
 Control/Status Reg area (CSR) data access method. More...
 
#define CR_SPACE_ID   0x001B
 CR/CSR space ID (VME64, VME64X, etc). More...
 
#define CR_ASCII_C   0x001F
 ASCII "C" (identifies this as CR space) More...
 
#define CR_ASCII_R   0x0023
 ASCII "R" (identifies this as CR space) More...
 
#define CR_IEEE_OUI   0x0027
 IEEE Organizationally Unique Identifier (OUI) More...
 
#define CR_IEEE_OUI_BYTES   3
 Number of bytes in manufacturer's OUI. More...
 
#define CR_BOARD_ID   0x0033
 Manufacturer's board ID. More...
 
#define CR_BOARD_ID_BYTES   4
 Number of bytes in manufacturer's OUI. More...
 
#define CR_REVISION_ID   0x0043
 Manufacturer's board revision ID. More...
 
#define CR_REVISION_ID_BYTES   4
 Number of bytes in board revision ID. More...
 
#define CR_ASCII_STRING   0x0053
 Offset to ASCII string (manufacturer-specific) More...
 
#define CR_PROGRAM_ID   0x007F
 Program ID code for CR space. More...
 
#define CR_BEG_UCR   0x0083
 Offset to start of manufacturer-defined CR space. More...
 
#define CR_END_UCR   0x008F
 Offset to end of manufacturer-defined CR space. More...
 
#define CR_BEG_UCSR_BYTES   3
 Number of bytes in User CSR starting offset. More...
 
#define CR_BEG_CRAM   0x009B
 Offset to start of Configuration RAM (CRAM) space. More...
 
#define CR_END_CRAM   0x00A7
 Offset to end of Configuration RAM (CRAM) space. More...
 
#define CR_BEG_UCSR   0x00B3
 Offset to start of manufacturer-defined CSR space. More...
 
#define CR_END_UCSR   0x00BF
 Offset to end of manufacturer-defined CSR space. More...
 
#define CR_BEG_SN   0x00CB
 Offset to beginning of board serial number. More...
 
#define CR_END_SN   0x00DF
 Offset to end of board serial number. More...
 
#define CR_SLAVE_CHAR   0x00E3
 Board's slave-mode characteristics. More...
 
#define CR_UD_SLAVE_CHAR   0x00E7
 Manufacturer-defined slave-mode characteristics. More...
 
#define CR_MASTER_CHAR   0x00EB
 Board's master-mode characteristics. More...
 
#define CR_UD_MASTER_CHAR   0x00EF
 Manufacturer-defined master-mode characteristics. More...
 
#define CR_IRQ_HANDLER_CAP   0x00F3
 Interrupt levels board can respond to (handle) More...
 
#define CR_IRQ_CAP   0x00F7
 Interrupt levels board can assert. More...
 
#define CR_CRAM_WIDTH   0x00FF
 Configuration RAM (CRAM) data access method) More...
 
#define CR_FN_DAWPR(N)   ( 0x0103 + (N)*0x04 ) /* N = 0 -> 7 */
 Start of Data Access Width Parameter (DAWPR) regs. More...
 
#define CR_DAWPR_BYTES   1 /* Number of bytes in a DAWPR register */
 
#define CR_FN_AMCAP(N)   ( 0x0123 + (N)*0x20 ) /* N = 0 -> 7 */
 Start of Address Mode Capability (AMCAP) registers. More...
 
#define CR_AMCAP_BYTES   8 /* Number of bytes in an AMCAP register */
 
#define CR_FN_XAMCAP(N)   ( 0x0223 + (N)*0x80 ) /* N = 0 -> 7 */
 Start of Extended Address Mode Cap (XAMCAP) registers. More...
 
#define CR_XAMCAP_BYTES   32 /* Number of bytes in an XAMCAP register */
 
#define CR_FN_ADEM(N)   ( 0x0623 + (N)*0x10 ) /* N = 0 -> 7 */
 Start of Address Decoder Mask (ADEM) registers. More...
 
#define CR_ADEM_BYTES   4 /* Number of bytes in an ADEM register */
 
#define CR_MASTER_DAWPR   0x06AF
 Master Data Access Width Parameter. More...
 
#define CR_MASTER_AMCAP   0x06B3
 Master Address Mode Capabilities (8 entries) More...
 
#define CR_MASTER_XAMCAP   0x06D3
 Master Extended Address Mode Capabilities (8 entries) More...
 
#define CR_SIZE   0x0750
 Size of CR space (in total bytes) More...
 
#define CR_BYTES   (CR_SIZE>>2)
 Number of bytes in CR space. More...
 
#define CSR_BAR   0x7ffff
 Base Address Register (MSB of our CR/CSR address) More...
 
#define CSR_BIT_SET   0x7fffb
 Bit Set Register (writing a 1 sets the control bit) More...
 
#define CSR_BIT_CLEAR   0x7fff7
 Bit Clear Register (writing a 1 clears the control bit) More...
 
#define CSR_CRAM_OWNER   0x7fff3
 Configuration RAM Owner Register (0 = not owned) More...
 
#define CSR_UD_BIT_SET   0x7ffef
 User-Defined Bit Set Register (for user-defined fns) More...
 
#define CSR_UD_BIT_CLEAR   0x7ffeb
 User-Defined Bit Clear Register (for user-defined fns) More...
 
#define CSR_FN_ADER(N)   (0x7ff63 + (N)*0x10) /* N = 0 -> 7 */
 Function N Address Decoder Compare Register (1st byte) More...
 
#define CSR_ADER_BYTES   4 /* Number of bytes in an ADER register */
 
#define CSR_BITSET_RESET_MODE   0x80
 Module is in reset mode. More...
 
#define CSR_BITSET_SYSFAIL_ENA   0x40
 SYSFAIL driver is enabled. More...
 
#define CSR_BITSET_MODULE_FAIL   0x20
 Module has failed. More...
 
#define CSR_BITSET_MODULE_ENA   0x10
 Module is enabled. More...
 
#define CSR_BITSET_BERR   0x08
 Module has asserted a Bus Error. More...
 
#define CSR_BITSET_CRAM_OWNED   0x04
 CRAM is owned. More...
 

Detailed Description

Common defininitions for registers found in the Configuration Rom (CR) on VME64 and VME64x cards.

These registers are addressed with the CSR address space.

The CR is a little strange in that all values are single bytes (D8), but still have 4 byte spacing. For example the Organizationaly Unique Identifier (OUI) is 3 bytes long. The first byte is offset 0x27, the second is 0x2B, and the third is 0x2F.

The following definitions were originally taken from the mrfEventSystem IOC written by: Jukka Pietarinen (Micro-Research Finland, Oy) Till Straumann (SLAC) Eric Bjorklund (LANSCE)

Corrected against 'The VMEBus Handbook' (Ch 5.6) ISBN 1-885731-08-6

Macro Definition Documentation

◆ CR_ADEM_BYTES

#define CR_ADEM_BYTES   4 /* Number of bytes in an ADEM register */

Definition at line 276 of file devcsr.h.

◆ CR_AMCAP_BYTES

#define CR_AMCAP_BYTES   8 /* Number of bytes in an AMCAP register */

Definition at line 266 of file devcsr.h.

◆ CR_ASCII_C

#define CR_ASCII_C   0x001F

ASCII "C" (identifies this as CR space)

Definition at line 220 of file devcsr.h.

◆ CR_ASCII_R

#define CR_ASCII_R   0x0023

ASCII "R" (identifies this as CR space)

Definition at line 221 of file devcsr.h.

◆ CR_ASCII_STRING

#define CR_ASCII_STRING   0x0053

Offset to ASCII string (manufacturer-specific)

Definition at line 229 of file devcsr.h.

◆ CR_BEG_CRAM

#define CR_BEG_CRAM   0x009B

Offset to start of Configuration RAM (CRAM) space.

Definition at line 238 of file devcsr.h.

◆ CR_BEG_SN

#define CR_BEG_SN   0x00CB

Offset to beginning of board serial number.

Definition at line 244 of file devcsr.h.

◆ CR_BEG_UCR

#define CR_BEG_UCR   0x0083

Offset to start of manufacturer-defined CR space.

Definition at line 234 of file devcsr.h.

◆ CR_BEG_UCSR

#define CR_BEG_UCSR   0x00B3

Offset to start of manufacturer-defined CSR space.

Definition at line 241 of file devcsr.h.

◆ CR_BEG_UCSR_BYTES

#define CR_BEG_UCSR_BYTES   3

Number of bytes in User CSR starting offset.

Definition at line 236 of file devcsr.h.

◆ CR_BOARD_ID

#define CR_BOARD_ID   0x0033

Manufacturer's board ID.

Definition at line 225 of file devcsr.h.

◆ CR_BOARD_ID_BYTES

#define CR_BOARD_ID_BYTES   4

Number of bytes in manufacturer's OUI.

Definition at line 226 of file devcsr.h.

◆ CR_BYTES

#define CR_BYTES   (CR_SIZE>>2)

Number of bytes in CR space.

Definition at line 286 of file devcsr.h.

◆ CR_CRAM_WIDTH

#define CR_CRAM_WIDTH   0x00FF

Configuration RAM (CRAM) data access method)

Definition at line 256 of file devcsr.h.

◆ CR_DATA_ACCESS_WIDTH

#define CR_DATA_ACCESS_WIDTH   0x0013

Configuration ROM area (CR) data access method.

Definition at line 216 of file devcsr.h.

◆ CR_DAWPR_BYTES

#define CR_DAWPR_BYTES   1 /* Number of bytes in a DAWPR register */

Definition at line 261 of file devcsr.h.

◆ CR_END_CRAM

#define CR_END_CRAM   0x00A7

Offset to end of Configuration RAM (CRAM) space.

Definition at line 239 of file devcsr.h.

◆ CR_END_SN

#define CR_END_SN   0x00DF

Offset to end of board serial number.

Definition at line 245 of file devcsr.h.

◆ CR_END_UCR

#define CR_END_UCR   0x008F

Offset to end of manufacturer-defined CR space.

Definition at line 235 of file devcsr.h.

◆ CR_END_UCSR

#define CR_END_UCSR   0x00BF

Offset to end of manufacturer-defined CSR space.

Definition at line 242 of file devcsr.h.

◆ CR_FN_ADEM

#define CR_FN_ADEM (   N)    ( 0x0623 + (N)*0x10 ) /* N = 0 -> 7 */

Start of Address Decoder Mask (ADEM) registers.

Definition at line 273 of file devcsr.h.

◆ CR_FN_AMCAP

#define CR_FN_AMCAP (   N)    ( 0x0123 + (N)*0x20 ) /* N = 0 -> 7 */

Start of Address Mode Capability (AMCAP) registers.

Definition at line 263 of file devcsr.h.

◆ CR_FN_DAWPR

#define CR_FN_DAWPR (   N)    ( 0x0103 + (N)*0x04 ) /* N = 0 -> 7 */

Start of Data Access Width Parameter (DAWPR) regs.

Definition at line 258 of file devcsr.h.

◆ CR_FN_XAMCAP

#define CR_FN_XAMCAP (   N)    ( 0x0223 + (N)*0x80 ) /* N = 0 -> 7 */

Start of Extended Address Mode Cap (XAMCAP) registers.

Definition at line 268 of file devcsr.h.

◆ CR_IEEE_OUI

#define CR_IEEE_OUI   0x0027

IEEE Organizationally Unique Identifier (OUI)

Definition at line 223 of file devcsr.h.

◆ CR_IEEE_OUI_BYTES

#define CR_IEEE_OUI_BYTES   3

Number of bytes in manufacturer's OUI.

Definition at line 224 of file devcsr.h.

◆ CR_IRQ_CAP

#define CR_IRQ_CAP   0x00F7

Interrupt levels board can assert.

Definition at line 254 of file devcsr.h.

◆ CR_IRQ_HANDLER_CAP

#define CR_IRQ_HANDLER_CAP   0x00F3

Interrupt levels board can respond to (handle)

Definition at line 253 of file devcsr.h.

◆ CR_MASTER_AMCAP

#define CR_MASTER_AMCAP   0x06B3

Master Address Mode Capabilities (8 entries)

Definition at line 279 of file devcsr.h.

◆ CR_MASTER_CHAR

#define CR_MASTER_CHAR   0x00EB

Board's master-mode characteristics.

Definition at line 250 of file devcsr.h.

◆ CR_MASTER_DAWPR

#define CR_MASTER_DAWPR   0x06AF

Master Data Access Width Parameter.

Definition at line 278 of file devcsr.h.

◆ CR_MASTER_XAMCAP

#define CR_MASTER_XAMCAP   0x06D3

Master Extended Address Mode Capabilities (8 entries)

Definition at line 280 of file devcsr.h.

◆ CR_PROGRAM_ID

#define CR_PROGRAM_ID   0x007F

Program ID code for CR space.

Definition at line 230 of file devcsr.h.

◆ CR_REVISION_ID

#define CR_REVISION_ID   0x0043

Manufacturer's board revision ID.

Definition at line 227 of file devcsr.h.

◆ CR_REVISION_ID_BYTES

#define CR_REVISION_ID_BYTES   4

Number of bytes in board revision ID.

Definition at line 228 of file devcsr.h.

◆ CR_ROM_CHECKSUM

#define CR_ROM_CHECKSUM   0x0003

8-bit checksum of Configuration ROM space

Definition at line 214 of file devcsr.h.

◆ CR_ROM_LENGTH

#define CR_ROM_LENGTH   0x0007

Number of bytes in Configuration ROM to checksum.

Definition at line 215 of file devcsr.h.

◆ CR_SIZE

#define CR_SIZE   0x0750

Size of CR space (in total bytes)

Definition at line 285 of file devcsr.h.

◆ CR_SLAVE_CHAR

#define CR_SLAVE_CHAR   0x00E3

Board's slave-mode characteristics.

Definition at line 247 of file devcsr.h.

◆ CR_SPACE_ID

#define CR_SPACE_ID   0x001B

CR/CSR space ID (VME64, VME64X, etc).

Definition at line 218 of file devcsr.h.

◆ CR_UD_MASTER_CHAR

#define CR_UD_MASTER_CHAR   0x00EF

Manufacturer-defined master-mode characteristics.

Definition at line 251 of file devcsr.h.

◆ CR_UD_SLAVE_CHAR

#define CR_UD_SLAVE_CHAR   0x00E7

Manufacturer-defined slave-mode characteristics.

Definition at line 248 of file devcsr.h.

◆ CR_XAMCAP_BYTES

#define CR_XAMCAP_BYTES   32 /* Number of bytes in an XAMCAP register */

Definition at line 271 of file devcsr.h.

◆ CSR_ADER_BYTES

#define CSR_ADER_BYTES   4 /* Number of bytes in an ADER register */

Definition at line 306 of file devcsr.h.

◆ CSR_BAR

#define CSR_BAR   0x7ffff

Base Address Register (MSB of our CR/CSR address)

Definition at line 294 of file devcsr.h.

◆ CSR_BIT_CLEAR

#define CSR_BIT_CLEAR   0x7fff7

Bit Clear Register (writing a 1 clears the control bit)

Definition at line 296 of file devcsr.h.

◆ CSR_BIT_SET

#define CSR_BIT_SET   0x7fffb

Bit Set Register (writing a 1 sets the control bit)

Definition at line 295 of file devcsr.h.

◆ CSR_BITSET_BERR

#define CSR_BITSET_BERR   0x08

Module has asserted a Bus Error.

Definition at line 315 of file devcsr.h.

◆ CSR_BITSET_CRAM_OWNED

#define CSR_BITSET_CRAM_OWNED   0x04

CRAM is owned.

Definition at line 316 of file devcsr.h.

◆ CSR_BITSET_MODULE_ENA

#define CSR_BITSET_MODULE_ENA   0x10

Module is enabled.

Definition at line 314 of file devcsr.h.

◆ CSR_BITSET_MODULE_FAIL

#define CSR_BITSET_MODULE_FAIL   0x20

Module has failed.

Definition at line 313 of file devcsr.h.

◆ CSR_BITSET_RESET_MODE

#define CSR_BITSET_RESET_MODE   0x80

Module is in reset mode.

Definition at line 311 of file devcsr.h.

◆ CSR_BITSET_SYSFAIL_ENA

#define CSR_BITSET_SYSFAIL_ENA   0x40

SYSFAIL driver is enabled.

Definition at line 312 of file devcsr.h.

◆ CSR_CRAM_OWNER

#define CSR_CRAM_OWNER   0x7fff3

Configuration RAM Owner Register (0 = not owned)

Definition at line 300 of file devcsr.h.

◆ CSR_DATA_ACCESS_WIDTH

#define CSR_DATA_ACCESS_WIDTH   0x0017

Control/Status Reg area (CSR) data access method.

Definition at line 217 of file devcsr.h.

◆ CSR_FN_ADER

#define CSR_FN_ADER (   N)    (0x7ff63 + (N)*0x10) /* N = 0 -> 7 */

Function N Address Decoder Compare Register (1st byte)

Definition at line 303 of file devcsr.h.

◆ CSR_UD_BIT_CLEAR

#define CSR_UD_BIT_CLEAR   0x7ffeb

User-Defined Bit Clear Register (for user-defined fns)

Definition at line 302 of file devcsr.h.

◆ CSR_UD_BIT_SET

#define CSR_UD_BIT_SET   0x7ffef

User-Defined Bit Set Register (for user-defined fns)

Definition at line 301 of file devcsr.h.